As semiconductor memory devices such as n-type DRAMs are being scaled down in dimensions, there is a continuous need to maintain a sufficiently high storage charge per capacitor unit area. In order to construct high density semiconductor memory devices in a reasonable sized chip area, the cell structures have changed from planar-type capacitors to either trench or stacked capacitors.
All efforts to increase capacitance without increasing planar area can be categorized into building three dimensional capacitor structures. Some examples of three dimensions capacitor structures existing in the art are trench capacitors and stacked capacitors. While solving the above problem of planar capacitors, trench capacitors and stacked capacitors have their own problems which limit their use and/or reliability.
One major problem associated with trench capacitors is that when the semiconductor memory device is beyond 16 Mbit the trench forming the capacitor region needs to be very deep. Technical problems and even theorized physical limitations in processing deep trenches are known. When the stacked capacitor approach is used to fabricate high density DRAMs, very complicated stacked capacitors are needed, such as fin structures and crown capacitors.
In recent years, in order to obtain denser arrays, smaller sized cells are required. This has led to trench capacitor devices wherein the transfer device is formed on a pillar below or above the capacitor. One major problem with these types of prior art trench capacitors is that the transfer device body is isolated from the substrate of the device. In other words, the body of the pillar (transfer device) is not continuous with the underlying substrate. The term "continuous" is used herein to denote that the middle region of the vertical transistor region is composed of the same material as the underlying substrate and thus in direct contact with the underlying substrate.
This isolation results in the device exhibiting the so-called floating body effect. As is known to those skilled in the art, devices that contain a floating body exhibit a higher degree of leakage than devices which do not have a floating body. This high degree of leakage results in decreased retention times for such devices; therefore such devices have limited use.
The above effects are created since prior art methods are unable to fabricate an outdiffused shallow junction region exhibiting the lowest possible resistance at the highest concentration of dopant material. In the prior art, a one step rapid thermal annealing (RTA) process is employed to form the outdiffused regions. While the prior art one step RTA is capable of forming a shallow penetration depth, it does not form an outdiffused region having the lowest possible resistance at the highest possible dopant concentration level. The formation of outdiffused shallow regions exhibiting the lowest possible resistance at the highest dopant concentration is of great importance in forming an outdiffused bitline structure having a continuous body.
In view of the above drawbacks with prior art methods, there is a continued need to develop new and improved methods of forming a shallow outdiffused buried bitline in a vertical semiconductor memory device which avoids the floating body effect observed with prior art vertical semiconductor memory devices, yet is capable of exhibiting the lowest possible resistance at the highest dopant concentration possible.